The present invention relates to the automatic skewing of addresses in a memory to change memory words with uncorrectable errors into memory words with errors that can be corrected by the error correction code protecting the memory.
Error correction and detection schemes for encoding data are known to detect more errors than they are capable of correcting. For instance, a 64 data bit word can be provided with a single error correction and a double error detection capability by using eight check bits which are stored on the same word location in memory as the 64 data bits. A failure of any single one of the 72 cells which store the data and check bits can be corrected by error correcting circuitry. This same circuitry can also be used to detect double errors existing in the word but generally will not correct these double errors. That is, if a single bit fails the particular defective bit can be identified and, therefore, corrected. However, if two bits fail the occurrence of the failure can be detected but the failing bits generally cannot be pinpointed and, therefore, cannot be corrected.
The term "generally" has been used in connection with double error correction because some of the single error correction codes do correct specific types of double errors such as errors in adjacent bit positions. However, not all double errors will occur in a correctable pattern. Therefore, to repeat what has already been said, an error correction system generally speaking will detect a greater number of errors than it has the capability of automatically correcting.
To take advantage of this capacity of an error correction code to detect more errors than it can correct, Beausoleil U.S. Pat. No. 3,644,902 suggests a means for changing errors that are detectable but uncorrectable into errors that are both detectable and correctable. In the Beausoleil patent, a memory unit is made up of a plurality of arrays each containing all the bits for one bit position in the memory unit. These arrays are each addressed through a decoder so that the proper bit of any word is selected from each array when the word is addressed. The Beausoleil patent suggests that, when multiple errors are to be avoided, circuitry be employed that permanently modifies the address supplied to the decoders to swap bits between words by physically wrapping the arrays and thereby change words with uncorrectable errors into words with correctable errors.
In Bossen et al U.S. Pat. No. 3,812,336, and in an article entitled "Address Reconfiguration for Large-Scale Integrated Memory Yield Inducement", appearing on page 1245 of the September 1973 issue of the IBM Technical Disclosure Bulletin, an address modification scheme was proposed to form electronic swapping of memory bits. In this scheme the address supplied to the decoder of any particular bit array is modified by logic circuitry as a function of data stored in a shift register associated with the particular bit position of the words in the memory unit. The logic circuitry controlled by each of the registers includes an Exclusive OR gate for each of the inputs of the decoder of the particular bit position. Each of the Exclusive OR gates accepts one digit of the word address and the output of one of the stages of the linear feedback shift register and supplied its output to one of the inputs of the decoder. In the IBM Technical Disclosure Bulletin article, the decoder input address of the bad bit is placed in the shift register so that when the bad bit is requested bit location 0 is accessed instead. In the Bossen et al patent, a different Galois field number is stored in each of the shift registers starting with zero in the shift register of the first bit position and proceeding in the Galois field number sequence to the highest number needed in the shift register of the last bit position. Each time a multiple error is detected, each of the shift registers, except the shift register for the first bit position, is shifted one Galois number. This assures that the detected multiple error will be eliminated by scattering the bits making up the failing word. As a result of this scattering, each of the falling bits end up in a different word changing the uncorrectable multiple error condition into a number of correctable single error conditions.
Test results pointing to the location of bad bits are used in Beausoleil Pat. Nos. 3,781,826 and 3,897,626 to divide chips into groups in accordance with the location of the failing bits. In U.S. Pat. No. 3,897,626, these chips are mounted on memory cards with all chips having a defective chip in a given chip section being mounted on a corresponding section of a card. The address wiring is then used to skew the errors so that no memory word contains more than one bad bit. If a failure is detected by an ECC system, an Exclusive ORing of two sections of the address of the failing word will locate the bad or suspicious bit.
In U.S. patent application Ser. No. 362,925, filed Mar. 29, 1982 and entitled "Deterministic Permutation Algorithm", the swapping of bits between different words of a memory is accomplished by using data on bad bits in the memory. The permutation of the bit addresses is done by an exclusionary process which identifies address combinations which result in alignment of bit failures that are uncorrectable by the error correction system of the memory and then limiting the selection process to other combinations. In the preferred embodiment, failures are categorized by type, such as chip, line or bit failure to determine uncorrectable combinations of failures. The bit addresses are then permuted in order of decreasing number of failures.